eFuse memory with Wishbone interface (efuse_wb_mem)¶
Module efuse_wb_mem¶
Description¶
This is a digital wrapper around Basic eFuse array block (efuse_array) providing a synchronous interface to the eFuse memory with Wishbone bus. Interface should be compatible with the classic Wishbone SoC bus standard. Wishbone addresses are per eFuse word, not per-byte. The maximum supported Wishbone clock frequency is 33 MHz.
It’s recommended to connect write_enable_i signal to the active-low POR reset to protect fuses during a power-up.
Verilog parameters¶
Parameter name |
Example value |
Description |
|---|---|---|
EFUSE_NWORDS |
64 |
Number of eFuse memory words, should be 2^WB_ADR_WIDTH |
EFUSE_WORD_WIDTH |
8 |
eFuse word width |
WB_ADR_WIDTH |
6 |
Wishbone address bus width |
WB_DAT_WIDTH |
8 |
Wishbone data buses width, should be equal to EFUSE_WORD_WIDTH |
WB_SEL_WIDTH |
(WB_DAT_WIDTH / 8) |
Wishbone write mask bus width |
Ports¶
Port name |
Direction |
Width |
Description |
|---|---|---|---|
wb_clk_i |
input |
1 |
Wishbone clock |
wb_rst_i |
input |
1 |
Active-high Wishbone reset |
wb_stb_i |
input |
1 |
Wishbone STB signal |
wb_cyc_i |
input |
1 |
Wishbone CYC signal |
wb_adr_i |
input |
[WB_ADR_WIDTH-1:0] |
Wishbone per-word address |
wb_dat_i |
input |
[WB_DAT_WIDTH-1:0] |
Wishbone data to write to eFuse |
wb_sel_i |
input |
[WB_SEL_WIDTH-1:0] |
Wishbone write mask |
wb_we_i |
input |
1 |
Wishbone write enable |
wb_dat_o |
output |
[WB_DAT_WIDTH-1:0] |
Wishbone data read from eFuse |
wb_ack_o |
output |
1 |
Wishbone acknowledge signal |
write_enable_i |
input |
1 |
Active-high asynchronous write-enable signal |